Fall 2008         M-Wed 2:00 PM -3:20  PM       Location: 112 Junkins

OFFICE HOURS
12:30PM-1:30PM in SIC or By appointment
 
DISABILITY ACCOMMODATIONS
Students needing academic accommodations for a disability must first contact Ms. Rebecca Marin, Coordinator, Services for Students with Disabilities (214-768-4557) to verify the disability and establish eligibility for accommodations.  They should then schedule an appointment with the professor to make appropriate arrangements.  (See University Policy No. 2.4.)

OBSERVANCE OF RELIGIOUS HOLIDAYS
Religiously observant students wishing to be absent on holidays that require missing class should notify their professors in writing at the beginning of the semester, and should discuss with them, in advance, acceptable ways of making up any work missed because of the absence.  (See University Policy No. 1.9.)

EXCUSED ABSENCES FOR UNIVERSITY EXTRACURRICULAR ACTIVITIES
Students participating in an officially sanctioned, scheduled University extracurricular activity should be given the opportunity to make up class assignments or other graded assignments missed as a result of their participation.  It is the responsibility of the student to make arrangements with the instructor prior to any missed scheduled examination or other missed assignment for making up the work.    (See the University Undergraduate Catalog).

CSE 3381 CO-REQUISITE LAB INSTRUCTOR/TEACHING ASSISTANT
Section N11, Laura Spenner, lspenner@engr.smu.edu
Section N12, John Howard, jjhoward@engr.smu.edu
Section N13, Kent Spenner, kspenner@engr.smu.edu

LAB INSTRUCTOR OFFICE HOURS
By appointment
 
TEXT
Digital Design, 4th Edition, M. Morris Mano and Michael D. Ciletti, Pearson Prentice-Hall, 2007, ISBN 0-13-198924-3.

REFERENCE
1.    Introduction to Logic Synthesis Using Verilog, R. B. Reese and M. A. Thornton, Morgan & Claypool Publishers, 2006, ISBN 10-1598291068.
2.    Verilog HDL Synthesis A Practical Primer, J. Bhasker, Star Galaxy Publishing, 1998, ISBN 0-9650391-5.
3.    Digital Design Principles & Practices, 3^rd Edition, John F. Wakerly, Prentice-Hall, 2001, ISBN 0-13-089896-1.
4.    Introduction to Digital Systems, M. Ercegovac, T. Lang, and J. H. Moreno, John Wiley & Sons, 1999, ISBN 0-471-52799-8.

CATALOG DESCRIPTION
Boolean functions. Logic gates.  Memory elements.  Synchronous and asynchronous circuits.  Shift registers and computers.  Logic and control.

PREREQUISITES
1. CSE 2240 - Assembly Language Programming and Machine Organization (Grade of C or better).
2. CSE 2353 - Discrete Computational Structures (Grade of C or better).

DATASHEETS
Texas Instruments
Fairchild (local)
Fairchild
Motorola
National Semiconductor (local)
National Semiconductor

ADMINISTRATION
Class Schedule
Grading Policy

TOPICS

• Number Systems
  • Binary, Octal, Hexadecimal
  • Base Conversions
  • Complements and Arithmetic Signs
• Codes, Storage and Logic
  • ASCII, BCD, Gray, and Parity
  • Registers and RTL
  • Logic Operations
• Boolean Algebra
  • Axioms, Theorems, and Properties
  • Canonical and Standard Forms
• Logic Gates
  • Positive and Negative Logic
  • Integrated Circuits and Families
• Gate-Level Minimization
  • Map Method
  • Two-level and Multi-level Circuits
• Verilog HDL Introduction
  • Discrete Event Simulation
  • Modules and Primitives
• Combinational Logic
  • Adders, Subtractors, and Comparators
  • Encoders and Decoders
  • Multiplexers and Demultiplexers
  • Verilog HDL for Combinational Logic
• Synchronous Sequential Logic
  • Latches and Flip-flops
  • Characteristic Tables and Equations
  • Timing Diagrams  
  • State Equations, Tables, and Diagrams
  • Mealy and Moore Models and HDL Descriptions
  • State Reduction and Assignment
  • Excitation Tables and FSM Synthesis
• Registers and Counters
  • Parallel and Serial I/O
  • Counters
  • Verilog HDL for Registers and Counters
• Memory and Programmable Logic
  • RAM and ROM Structure
  • Address Decoding
  • Programmable Logic Structures
  • Timing Diagrams
• Register Transfer Level (RTL) Descriptions
  • Basic Notation
  • RTL in Verilog HDL