IEEE Solid State Circuit Society
Dallas Chapter

Greetings from the Chair:

Welcome to the new IEEE Solid State Circuit Society in Dallas!! As the chair of the Dallas Chapter, I like to extend an invitation to everyone in the Dallas area with an interest in Solid State Circuits. We have one meeting scheduled every month from September 2000 to June 2001. The monthly meeting typically features a seminar by a speaker on a topic of interest to the SSCS members.

Our monthly seminars are open to everyone. It is our hope to continue to provide quality seminars as well as networking opportunities for members in the greater Dallas area.

Your comments or suggestions for a better SSCS are greatly appreciated.

Yin Hu (hu@ti.com)

Upcoming monthly seminars:

Title: "Mixed-Signal Design for Test"

Abstract:

Digital Design for Test (DfT) is often implemented using standardized methodologies, such as scan. Scan testing allows arbitrary designs to be tested using a standard development flow that allows automated insertion of digital DfT structures and automated test vector generation. Mixed-signal DfT is a more complicated issue, since failures in mixed-signal circuits are often caused by non-catastrophic defects such as minor process variations. Analog and mixed-signal DfT has mostly been restricted to ad hoc methods and circuits that must be evaulated for suitability on a case-by-case basis. However, a number of commonly used DfT features can be applied (with care) to most mixed-signal circuits. This presentation is based on Chapter 14 of the textbook "An Introduction to Mixed-Signal IC Test and Measurement" by Mark Burns and Gordon Roberts. The table of contents for this chapter is listed below: 
14.1. Overview
14.2. Advantages of DfT
14.3. Digital Scan
14.4. Digital BIST
14.5. Digital DfT for Mixed-Signal Circuits
14.6. Mixed-Signal Boundary Scan and BIST
14.7. Ad Hoc Mixed-Signal DfT
14.8. Subtle Forms of Analog DFT
14.9. IDDQ
14.10. Summary

Speaker:

Mark Burns, Texas Instruments

Biography:

Mark Burns is a TI Fellow at Texas Instruments, Inc, specializing in the field of mixed-signal test and testability. Mark spent 15 years in the mixed-signal testing field at LTX corporation and

Date:

Thursday, May 24, 2001

Time:

11:30am, Social/Refreshments
12:00-1:00pm, Seminar

Place:

Texas Instruments Forest Lane Auditorium. Non-TI employees: park near the main entrance at the southeast side of the campus and enter the South Lobby. The receptionist can direct you to the auditorium.

Address:

12500 TI Boulevard, Dallas, TX 75243

Title: "New Exciting Development of Low Power and High Speed Arithmetic Circuits"

Abstract:

In this talk, we present recent exciting development in low power and high speed arithmetic circuits including adders, multipliers, and residue number systems. Our results are quite fundmantal and different from the ones you have learned in any textbooks.

We start with a summary of arithmetic circuits studied from various perspectives. The numbers can be represented in 2's complement or signed redundant numbers. The basic logic operations in the implementation can be AND-OR two level gates, MUX, complex gates, or pass transistors. The circuits can be designed for different objectives such as high speed, low power, or small area, and implemented in various technologies such as Bipolar, dynamic logic, Domino logic, complement CMOS, and BiCMOS. Our results are useful for all those aspects.

We then present many new kinds of single bit adders, different from the complementary CMOS full adders using 28 or 40 transistors. For example, we designed full adders using only 10 transistors or 5 MUX. We have also collected more than 34 different full adders published in the literature and done comprehensive performance study in power and speed.

For multiple-bit adders, the addition algorithms can be classified as carry Look-ahead adder, conditional sum adder, carry skip adder, carry select adder, prefix adder, and block hybrid adder with group carries. In this talk, we present a unified framework and techniques to simplify almost all previous addition algorithms including the conditional sum adder, carry-select adder, block based hybrid adder, and prefix adder. Therefore we are able to improve all but the carry-skip adders. Moreover, we will show how to improve some famous prefix adders such as the Brent-Kung's adders.

Finally, we present the New Chinese Remainder Theorems which improve the conventional Chinese Remainder Theorem developed by Gauss in 1801, which is the base for the Residue Number systems.

Speaker:

Dr. Yuke Wang, Department of Computer Science, University of Texas at Dallas

Biography:

Dr. Yuke Wang, currently an Assistant Professor at the Computer Science Department, University of Texas at Dallas, has been active in the area of VLSI design of circuits and systems for DSP and communication for many years. He has been a visiting Assistant Professor of University of Minnesota during the summer of 1999 and the summer of 2000. He has been a visiting Assistant Professor at the University of Maryland at the summer of 2000.

During 1996-2000, Dr. Wang has worked and co-authored papers with more than 20 people, including many IEEE/ACM Transactions papers such as IEEE Trans. on Computers, IEEE Trans. on Circuits and Systems, IEEE Trans. on CAD, IEEE Trans. on Signal Processing, and ACM Trans. on Design Automation of Electronic Systems.

Date:

Thursday, June 21, 2001

Time:

11:30am, Social/Refreshments
12:00-1:00pm, Seminar

Place:

Texas Instruments Forest Lane Auditorium. Non-TI employees: park near the main entrance at the southeast side of the campus and enter the South Lobby. The receptionist can direct you to the auditorium.

Address:

12500 TI Boulevard, Dallas, TX 75243

SSCS Webpage:

http://www.seas.smu.edu/orgs/ssc

Contact:

hu@ti.com