Astro Interactive Ultra (AIU) is used for routing at the top level to connect the standard cells blocks with IP, RAM and other analog blocks to produce an efficient routing pattern.
DesignWare Memory Models are pre-verified simulation models of memory devices. The DesignWare Memory Models are built on top of proven Synopsys memory model technology thus ensuring model accuracy, quality and reliability.
Parses Verilog files to extract top-level module input and output ports - Parse a set of Verilog behavioral files to find all the Input/Output statements for a specific module which is going to be used in ESP-CV. The statements are used to create an initial config file.
ESP-BV symbolic simulator - ESP-BV provides functional simulation of large highly repetitive designs, represented all levels of abstraction from Verilog behavioral, RTL, and gates, to transistor level netlist.
ESP Coverage merge program - This program merges symbolic coverage results from different simulation runs of the SAME DESIGN and generates a new coverage data base, which can be reported on by the espcov program.
ESP-CV symbolic simulator - ESP-CV verifies that two different design representations are functionally equivalent. These designs may be described as Verilog behavioral models, RTL, UDP’s, gates, transistors, or SPICE netlist views.
ESP-LV Library Verification utility - This program checks the functional equivalence between two implementations of the same design. Typically the Spice netlist and the RTL behavioral model. If you provide a cell list, all of the cells in the list will be checked unless you specify just one of the cells in the list to be verified. A directory will be created for each design being checked.
Generate a simulation performance report for a previous simulation run using the -profile command line option. When simulating with the -profile command line option, the file esp.prof is created. The name of that file must be passed to this utility.
ESP test bench generator - generate a test bench for ESP-CV to implement the verification of a reference model (usually Verilog RTL) to an implementation model (usually a SPICE netlist)
